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local-powerpc8xx-dcbz.diff
--- a/sysdeps/unix/sysv/linux/powerpc/dl-auxv.h +++ b/sysdeps/unix/sysv/linux/powerpc/dl-auxv.h @@ -23,8 +23,25 @@ int GLRO(dl_cache_line_size); #endif /* Scan the Aux Vector for the "Data Cache Block Size" entry and assign it - to dl_cache_line_size. */ -#define DL_PLATFORM_AUXV \ + to dl_cache_line_size. We have to detect 8xx processors, which + have buggy dcbz implementations that cannot report page faults + correctly. That requires reading SPR, which is a privileged + operation. Fortunately 2.2.18 and later emulates PowerPC mfspr + reads from the PVR register. */ +#ifndef __powerpc64__ + #define DL_PLATFORM_AUXV \ + case AT_DCACHEBSIZE: \ + { \ + unsigned pvr = 0; \ + asm ("mfspr %0, 287" : "=r" (pvr)); \ + if ((pvr & 0xffff0000) == 0x00500000) \ + break; \ + } \ + GLRO(dl_cache_line_size) = av->a_un.a_val; \ + break; +#else + #define DL_PLATFORM_AUXV \ case AT_DCACHEBSIZE: \ GLRO(dl_cache_line_size) = av->a_un.a_val; \ break; +#endif